head	1.1;
access;
symbols;
locks
	pnixon:1.1; strict;
comment	@# @;


1.1
date	2002.05.04.16.22.40;	author pnixoneast;	state Exp;
branches;
next	;


desc
@none
@


1.1
log
@none
@
text
@   1 Integration 1 milestones (think about when these will be completed by , add dependences as well):
      * Timing env - all flows proven.
         * Parsing constraints out of spec.
         * Start with Summary script 
         * Web based to follow.
      * DFT env - all flows proven.
         * Getting started with Jbus .
         * MBIST.
         * Lbist.
         * Scan insertion.
      * Top Level
         * Boundary scan.
         * Lbist/MBIST/Scan
         * Tap generation.
         * Net-list generation.
            * Cores
            * Chip
            * verif
         * Equiv
            * RTL to gates
            * gates to gates
      * Physical Design - all flows proven.
         * Flow here (LSI flow running at Sun).
         * DFT/ high fanout nets/Scan reorder 
         * Equiv.
         * IO timing.
         * Clocking.
         * ECOs
      * Synth Design - all flows proven
         * Obtain RTL test cases of difficult physical designs from eagle.
         * Push button synth for designers.
            * Cores with logic test.
            * Core without logic test.
            * block level.
            * Dual cores.
            * Report automation.
            * Directory structure.
      * Vectors - all flows proven.
         * Capture.
         * Munge.
         * Tester formating.
         * Replay.
         * DTL 
         * 3GIO
         * Misc
            * Power
            * LSI
            * DFT
            * IDDQ
      * Power
         * RTL
         * Gates
         * Back-annotation
         * Test(s)
            * DFT Lbist wait states.
            * Full tilt boogie
            * Estar
   2 Tomatillo full integration flow (Come up with dates/durations for the following and dependences).
      * Synth/DFT insertion complete.
      * Physical design complete.
      * Timing flow complete (generated from LV).
      * Simulation env (DFT test bench only)
         * RTL
         * Gates
         * Back-annotation SDF's
         * Equiv
         * Power
   3 Individual updates:
      * DFT
      * Synth
      * PD
         * Jbus 
         * IB 
      * Timing
      * Top level/Hier
      * Misc


@