69 lines
2.7 KiB
Plaintext
69 lines
2.7 KiB
Plaintext
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Options
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1. Logicvision Embedded core test
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Advantages:
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- Fully supported automated tool flow.
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Disadvantages:
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- Costs way too much, not enough licenses per chip.
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2. Home-built PRPG/MISR
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Description:
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Logicvision used to construct top-level with logicbist and
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TAP controllers. Each core is stitched and then wrapped with
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a home-built "p1500" wrapper that includes a home-built
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logicbist controller. Software is used to generate vectors
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for fault-simulation (within the logicvision tools). The
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expected output vectors from LV is used by more software to
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calculate the expected signature for the MISR portion of
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the design.
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Advantages:
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- Get the hierarchical bist without paying for LV's.
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- Total control over the design, whether done by automated tool
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or not.
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- Offer the choice of programmable polynomials and signatures, with
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a default polynomial/signature pair for power-on self-test.
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- Predictable interface to the BIST controller.
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- Can use existing LBIST controller for top-level logic and
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interconnect BIST.
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Disadvantages:
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- Can't use LV to generate verilog testbenches and WGL for
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core logic-bist.
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- Have to write tools to generate vectors for input to LV's fault
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simulation for the core.
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- Have to write tools to generate testbenches for verilog and WGL.
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- Shared-isolation ring (used for core isolation) is not available
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in the standard release of the LV tools; Only available with the
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embedded core test version.
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- Have to hand-stitch up each core isolation ring, if shared isolation is
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required; Could use home-grown tools for this, or just make requirements
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of designers to do so ahead of time.
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3. Shared LBIST controller
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Description:
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Use the top-level logicbist controller to run logicbist against
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individual cores one at a time, and then run interconnect bist against
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the top-level interconnect and logic.
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Advantages:
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- Can use the LV tool suite to generate all test patterns and testbenches.
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Disadvantages:
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- Requires hand-tuning of clocks and paths to/from the logicbist controller.
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- Requires clock architecture that LV tools may not like, and may not be
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automatically closable in timing-driven layout.
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- Requires flops floating at top-level for pipelining control and data lines
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between the global bist controller and each core.
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- Requires hacking up the netlist (to remove all cores except the one under
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test, or all cores in the case of top-level interconnect testing) to
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generate test vectors.
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