104 lines
2.3 KiB
Plaintext
104 lines
2.3 KiB
Plaintext
head 1.1;
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access;
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symbols;
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locks
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pnixon:1.1; strict;
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comment @# @;
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1.1
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date 2002.05.04.16.22.40; author pnixoneast; state Exp;
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branches;
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next ;
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desc
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@none
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@
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1.1
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log
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@none
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@
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text
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@ 1 Integration 1 milestones (think about when these will be completed by , add dependences as well):
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* Timing env - all flows proven.
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* Parsing constraints out of spec.
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* Start with Summary script
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* Web based to follow.
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* DFT env - all flows proven.
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* Getting started with Jbus .
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* MBIST.
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* Lbist.
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* Scan insertion.
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* Top Level
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* Boundary scan.
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* Lbist/MBIST/Scan
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* Tap generation.
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* Net-list generation.
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* Cores
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* Chip
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* verif
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* Equiv
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* RTL to gates
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* gates to gates
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* Physical Design - all flows proven.
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* Flow here (LSI flow running at Sun).
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* DFT/ high fanout nets/Scan reorder
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* Equiv.
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* IO timing.
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* Clocking.
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* ECOs
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* Synth Design - all flows proven
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* Obtain RTL test cases of difficult physical designs from eagle.
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* Push button synth for designers.
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* Cores with logic test.
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* Core without logic test.
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* block level.
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* Dual cores.
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* Report automation.
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* Directory structure.
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* Vectors - all flows proven.
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* Capture.
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* Munge.
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* Tester formating.
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* Replay.
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* DTL
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* 3GIO
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* Misc
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* Power
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* LSI
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* DFT
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* IDDQ
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* Power
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* RTL
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* Gates
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* Back-annotation
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* Test(s)
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* DFT Lbist wait states.
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* Full tilt boogie
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* Estar
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2 Tomatillo full integration flow (Come up with dates/durations for the following and dependences).
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* Synth/DFT insertion complete.
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* Physical design complete.
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* Timing flow complete (generated from LV).
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* Simulation env (DFT test bench only)
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* RTL
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* Gates
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* Back-annotation SDF's
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* Equiv
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* Power
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3 Individual updates:
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* DFT
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* Synth
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* PD
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* Jbus
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* IB
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* Timing
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* Top level/Hier
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* Misc
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@
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